Thursday, September 10, 2009

Overview of CPU design

CPU design focuses on these areas:
datapaths (such as ALUs and pipelines)
control unit: logic which controls the datapaths
Memory components such as register files, caches
Clock circuitry such as clock drivers, PLLs, clock distribution networks
Pad transceiver circuitry
Logic gate cell library which is used to implement the logic
CPUs designed for high-performance markets might require custom designs for each of these items to achieve frequency, power-dissipation, and chip-area goals.
CPUs designed for lower performance markets might lessen the implementation burden by:
Acquiring some of these items by purchasing them as intellectual property
Use control logic implementation techniques (logic synthesis using CAD tools) to implement the other components - datapaths, register files, clocks
Common logic styles used in CPU design include:
Unstructured random logic
Finite-state machines
Microprogramming (common from 1965 to 1985, no longer common except for CISC CPUs)
Programmable logic array (common in the 1980s, no longer common)
Device types used to implement the logic include:
Transistor-transistor logic Small Scale Integration jelly-bean logic chips - no longer used for CPUs
Programmable Array Logic and Programmable logic devices - no longer used for CPUs
Emitter-coupled logic (ECL) gate arrays - no longer common
CMOS gate arrays - no longer used for CPUs
CMOS ASICs - what's commonly used today, they're so common that the term ASIC is not used for CPUs
Field-programmable gate arrays (FPGA) - common for soft microprocessors, and more or less required for reconfigurable computing
A CPU design project generally has these major tasks:
Programmer-visible instruction set architecture, which can be implemented by a variety of microarchitectures
Architectural study and performance modeling in ANSI C/C++ or SystemC
High-level synthesis (HLS) or RTL (eg. logic) implementation
RTL Verification
Circuit design of speed critical components (caches, registers, ALUs)
Logic synthesis or logic-gate-level design
Timing analysis to confirm that all logic and circuits will run at the specified operating frequency
Physical design including floorplanning, place and route of logic gates
Checking that RTL, gate-level, transistor-level and physical-level representations are equivalent
Checks for signal integrity, chip manufacturability
As with most complex electronic designs, the logic verification effort (proving that the design does not have bugs) now dominates the project schedule of a CPU.
Key CPU architectural innovations include index register, cache, virtual memory, instruction pipelining, superscalar, CISC, RISC, virtual machine, emulators, microprogram, and stack.

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