Wednesday, August 12, 2009

microcontroller Description

i8085 microarchitecture.
The 8085 is a conventional von Neumann design based on the Intel 8080. Unlike the 8080 it had no state signals multiplexed onto the data bus, but the 8-bit data bus was instead multiplexed with the lower part of the 16-bit address bus (in order to limit the number of pins to 40). The processor was designed using nMOS circuitry and the later "H" versions were implemented in Intel's enhanced nMOS process called HMOS, originally developed for fast static RAM products. The 8085 used approximately 6,500 transistors[1].
The 8085 incorporated the functionality of the 8224 (clock generator) and the 8228 (system controller), increasing the level of integration. A downside compared to similar contemporary designs (such as the Z80) was the fact that the buses required demultiplexing, however, address latches in the Intel 8155, 8355, and 8755 memory chips allowed a direct interface, so an 8085 along with these chips was almost a complete system.
The 8085 had extensions to support new interrupts: It had three maskable interrupts (RST 7.5, RST 6.5 and RST 5.5), one Non-Maskable interrupt (TRAP), and one externally serviced interrupt (INTR). The RST n.5 interrupts refer to actual pins on the processor-a feature which permitted simple systems to avoid the cost of a separate interrupt controller.
Like the 8080, the 8085 could accommodate slower memories through externally generated wait states (pin 35, READY), and had provisions for Direct Memory Access (DMA) using HOLD and HLDA signals (pins 39 and 38). An improvement over the 8080 was that the 8085 can itself drive a piezoelectric crystal directly connected to it, and a built in clock generator generates the internal high amplitude two-phase clock signals at half the crystal frequency (a 6.14 MHz crystal would yield a 3.07 MHz clock for instance).

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